View MAX9206_223539.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-2130; Rev 0; 8/01
KIT ATION EVALU ABLE AVAIL
10-Bit Bus LVDS Deserializers
Features
o Stand-Alone Deserializer (vs. SERDES) Ideal for Unidirectional Links o Automatic Clock Recovery o Allow Hot Insertion and Synchronization Without System Interruption o BLVDS Serial Input Rated for Point-to-Point and Bus Applications o Fast Pseudorandom Lock o Wide Reference Clock Input Range 16MHz to 40MHz (MAX9206) 40MHz to 60MHz (MAX9208) o High 720ps (p-p) Jitter Tolerance (MAX9206) o Low 30mA Supply Current (MAX9206 at 16MHz) o 10-Bit Parallel LVCMOS/LVTTL Output o Up to 600Mbps Throughput (MAX9208) o Programmable Output Strobe Edge o Pin Compatible to DS92LV1212A and DS92LV1224
General Description
The MAX9206/MAX9208 deserializers transform a highspeed serial bus low-voltage differential signaling (BLVDS) data stream into 10-bit-wide parallel LVCMOS/ LVTTL data and clock. The deserializers pair with serializers such as the MAX9205/MAX9207, which generate a serial BLVDS signal from 10-bit-wide parallel data. The serializer/deserializer combination reduces interconnect, simplifies PC board layout, and reduces board size. The MAX9206/MAX9208 receive serial data at 400Mbps and 600Mbps, respectively, over board traces or twisted-pair cables. These devices combine frequency lock, bit lock, and frame lock to produce a parallel-rate clock and word-aligned 10-bit data. Serialization eliminates parallel bus clock-to-data and data-to-data skew. A power-down mode reduces typical supply current to less than 600A. Upon power-up (applying power or driving PWRDN high), the MAX9206/MAX9208 establish lock after receiving synchronization signals or serial data from the MAX9205/MAX9207. An output enable allows the outputs to be disabled, putting the parallel data outputs and recovered output clock into a highimpedance state without losing lock. The MAX9206/MAX9208 operate from a single +3.3V supply and are specified for operation from -40C to +85C. The MAX9206/MAX9208 are available in 28-pin SSOP packages.
MAX9206/MAX9208
Ordering Information
PART MAX9206EAI MAX9208EAI TEMP. RANGE -40C to +85C -40C to +85C REF CLOCK PINRANGE (MHz) PACKAGE 16 to 40 40 to 60 28 SSOP 28 SSOP
Applications
Cellular Phone Base Stations Add/Drop Muxes Digital Cross-Connects DSLAMs Network Switches and Routers Backplane Interconnect
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
PARALLEL-TO-SERIAL OUT+ 100 OUTPC BOARD OR TWISTED PAIR EN PWRDN MAX9205 MAX9207 MAX9206 MAX9208 PLL RI+ 100 RISERIAL-TO-PARALLEL BUS LVDS OUTPUT LATCH INPUT LATCH
10 IN_ TCLK_R/F TCLK
10 ROUT_
REFCLK TIMING AND CONTROL CLOCK RECOVERY REN LOCK RCLK RCLK_R/F
PLL SYNC 1 SYNC 2
TIMING AND CONTROL
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
10-Bit Bus LVDS Deserializers MAX9206/MAX9208
ABSOLUTE MAXIMUM RATINGS
AVCC, DVCC to AGND, DGND .................................-0.3V to +4V RI+, RI- to AGND, DGND .........................................-0.3V to +4V All Other Pins to DGND ..............................-0.3V to DVCC + 0.3V ROUT_ Short-Circuit Duration (Note 1) ......................Continuous Continuous Power Dissipation (TA = +70C) 28-Pin SSOP (derate 9.5mW/C above +70C) ..........762mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Rating (Human Body Model, RI+, RI-) .........................8kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(AVCC = DVCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.2V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40C to +85C, unless otherwise noted. Typical values are at AVCC = DVCC = +3.3V, VCM = 1.1V, |VID| = 0.2V, TA = +25C.) (Notes 2, 3)
PARAMETER POWER SUPPLY CL = 15pF, worst-case pattern, Figure 1 PWRDWN = low 2.0 0 VIN = 0, AVCC, or DVCC IOH = -5mA IOL = 5mA VROUT_ = 0 PWRDN = low, VROUT_ = VRCLK = V LOCK = 0, AVCC, or DVCC -15 2.2 0 -15 -1 2.9 0.33 -38 MAX9206 MAX9208 16MHz 40MHz 40MHz 60MHz 30 57 55 80 45 75 75 100 1 VCC 0.8 15 VCC 0.5 -85 1 mA V V A V V mA A mA SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current
ICC
Power-Down Supply Current High-Level Input Voltage Low-Level Input Voltage Input Current High-Level Output Voltage Low-Level Output Voltage Output Short-Circuit Current Output High-Impedance Current BLVDS SERIAL INPUT (RI+, RI-) Differential Input High Threshold Differential Input Low Threshold Input Current Power-Off Input Current Input Resistor 1 Input Resistor 2
ICCX VIH VIL IIN VOH VOL IOS IOZ
LVCMOS/LVTTL LOGIC INPUTS (REN, REFCLK, RCLK_R/F, PWRDN)
LVCMOS/LVTTL LOGIC OUTPUTS (ROUT_, RCLK, LOCK)
VTH VTL IRI+, IRIIRI+OFF, IRI-OFF RIN1 RIN2 0.1V |VID| 0.45V 0.45V < |VID| 0.6V 0.1V |VID| 0.45V, AVCC = DVCC = 0 0.45V < |VID| 0.6V, AVCC = DVCC = 0 AVCC = DVCC = 3.6V or 0, Figure 2 AVCC = DVCC = 3.6V or 0, Figure 2 -100 -64 -82 -64 -82 4 150
9 -9
100 64 82 64 82
mV mV A A k k
2
_______________________________________________________________________________________
10-Bit Bus LVDS Deserializers MAX9206/MAX9208
AC ELECTRICAL CHARACTERISTICS
(AVCC = DVCC = +3.0V to +3.6V, CL = 15pF, differential input voltage |VID| = 0.15V to 1.2V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40C to +85C, unless otherwise noted. Typical values are at AVCC = DVCC = +3.3V, VCM = +1.1V, |VID| = 0.2V, TA = +25C.) (Notes 4, 5)
PARAMETER SYMBOL MAX9206 MAX9208 MAX9206 MAX9208 CONDITIONS MIN 16 40 -200 25 16.666 30 50 3 MAX9206 MAX9208 Figure 3 Figure 3 MAX9206, 40MHz Deserializer Delay tDD Figure 4 MAX9208, 60MHz ROUT_ Data Valid Before RCLK ROUT_ Data Valid After RCLK RCLK Duty Cycle OUTPUT High-to-High Impedance Delay OUTPUT Low-to-High Impedance Delay OUTPUT High-Impedance to High-State Delay OUTPUT High-Impedance to Low-State Delay PLL Lock Time (from PWRDN Transition High) tROS tROH tRDC tHZR tLZR tZHR tZLR CL = 5pF, Figure 6 CL = 5pF, Figure 6 CL = 5pF, Figure 6 CL = 5pF, Figure 6 Sync patterns at input; supply and REFCLK stable; measured from PWRDN transition high to LOCK transition low; Figure 7 Figure 5 Figure 5 25 16.666 1.5 2 TYP MAX 40 60 200 62.5 25 70 6 62.5 25 3 3 UNITS
REFERENCE CLOCK TIMING REQUIREMENTS (REFCLK) REFCLK Frequency REFCLK Frequency Variation REFCLK Period REFCLK Duty Cycle REFCLK Input Transition Time SWITCHING CHARACTERISTICS Recovered Clock (RCLK) Period (Note 6) Low-to-High Transition Time High-to-Low Transition Time tRCP tCLH tCHL ns ns ns fRFF RFFV tRFCP RFDC tRFTT MHz ppm ns % ns
1.75 x tRCP 1.75 x tRCP 1.75 x tRCP +2 + 3.3 + 6.5 1.75 x tRCP 1.75 x tRCP 1.75 x tRCP + 1.1 + 3.3 + 5.6 0.4 x tRCP 0.4 x tRCP 43 0.5 x tRCP 0.5 x tRCP 50 57 8 8 6 6 ns
ns ns % ns ns ns ns
tDSR1
(2048 + 42) x tRFCP
ns
_______________________________________________________________________________________
3
10-Bit Bus LVDS Deserializers MAX9206/MAX9208
AC ELECTRICAL CHARACTERISTICS (continued)
(AVCC = DVCC = +3.0V to +3.6V, CL = 15pF, differential input voltage |VID| = 0.15V to 1.2V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40C to +85C, unless otherwise noted. Typical values are at AVCC = DVCC = +3.3V, VCM = +1.1V, |VID| = 0.2V, TA = +25C.) (Notes 4, 5)
PARAMETER PLL Lock Time (from Start of Sync Patterns) LOCK High-Z to High-State Delay SYMBOL CONDITIONS PLL locked to stable REFCLK; supply stable; static input; measured from start of sync patterns at input to LOCK transition low; Figure 8 Figure 7 MAX9206 Input Jitter Tolerance tJT Figure 9 MAX9208 16MHz 40MHz 40MHz 60MHz 1300 720 720 320 ps MIN TYP MAX UNITS
tDSR2
42 x tRFCP
ns
tZHLK
30
ns
Note 1: Short one output at a time. Do not exceed the Absolute Maximum continuous power dissipation. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Voltages are referenced to ground except VTH, VTL, and VID, which are differential input voltages. Note 3: DC parameters are production tested at TA = +25C and guaranteed by design and characterization over operating temperature range. Note 4: AC parameters guaranteed by design and characterization. Note 5: CL includes scope probe and test jig capacitance. Note 6: tRCP is determined by the period of TCLK, which is the reference clock of the serializer driving the deserializer. The frequency of TCLK must be within 400ppm of the REFCLK frequency.
4
_______________________________________________________________________________________
10-Bit Bus LVDS Deserializers
Pin Description
PIN 1, 12, 13 2 3 4, 11 5 6 7 8 9 10 14, 20, 22 15-19, 24-28 21, 23 NAME AGND RCLK_R/F REFCLK AVCC RI+ RIPWRDN REN RCLK LOCK DGND ROUT9- ROUT0 DVCC Analog Ground Strobe Edge Select for Recovered Clock (RCLK). LVTTL/LVCMOS level input. Drive RCLK_ R/F high to strobe ROUT_ on the rising edge of RCLK. Drive RCLK_R/F low to strobe ROUT_ on the falling edge of RCLK. Reference Clock for PLL. LVTTL/LVCMOS level input. Analog Power Supply. Bypass AVCC with a 0.1F and a 0.001F capacitor to AGND. Serial Data Input. Noninverting BLVDS differential input. Serial Data Input. Inverting BLVDS differential input. Power Down. LVTTL/LVCMOS level input. Drive PWRDN low to stop the PLL and put ROUT_, LOCK, and RCLK in high impedance. Output Enable. LVTTL/LVCMOS level input. Drive REN low to put ROUT_ and RCLK in high impedance. LOCK remains active, indicating the status of the serial input. Recovered Clock. LVTTL/LVCMOS level output. Use RCLK to strobe ROUT_. Lock Indicator. LVTTL/LVCMOS level output. LOCK goes low when the PLL has achieved frequency and phase lock to the serial input, and the framing bits have been identified. Digital Ground Parallel Output Data. LVTTL/LVCMOS level outputs. ROUT_ is valid on the second selected strobe edge of RCLK after LOCK goes low. Digital Power Supply. Bypass DVCC with a 0.1F and a 0.001F capacitor to DGND. FUNCTION
MAX9206/MAX9208
Test Circuits/Timing Diagrams
START BIT RI 0 1 2 3 4 5 6 7 8 9 START BIT END BIT 0 1 2 3 4 5 6 7 8 9 START BIT 0 1 2
END BIT
TDD RCLK ODD ROUT RCLK_R/F = HIGH
EVEN ROUT
Figure 1. Worst-Case ICC Test Pattern _______________________________________________________________________________________ 5
10-Bit Bus LVDS Deserializers MAX9206/MAX9208
Test Circuits/Timing Diagrams (continued)
VCC RIN2
LVCMOS/LVTTL OUTPUT
CL 15pF
VCC - 0.3V RI+ RIN1 TO DESERIALIZING CIRCUITRY
80%
80%
RIN1 RI-
20% tCLH tCHL
20%
Figure 2. Input Fail-Safe Circuit
START BIT RI RCLK ROUT_ RCLK_R/F = HIGH SYMBOL N-1 0 1 START SYMBOL N 2 3 4 5 6 7 8 END BIT 9 BIT 0 tDD
Figure 3. LVCMOS/LVTTL Output Load and Transition Times
START END BIT 9 BIT 0
1
2
SYMBOL N+1 3456
7
8
1
2
SYMBOL N
Figure 4. Input-to-Output Delay
+7V FOR tLZR AND tZLR OPEN FOR tHZR AND tZHR
500 450
SCOPE 50
RCLK RCLK_R/F = LOW RCLK RCLK_R/F = HIGH tROS DATA VALID BEFORE RCLK
50%
CL
50% tROH DATA VALID AFTER RCLK
ROUT_ RCLK VOL VOH VOH -0.5V tHZR tZHR REN tLZR VOL +0.5V
1.5V tZLR
ROUT_
Figure 5. Data Valid Times
Figure 6. High-Impedance Test Circuit and Timing 6 ______________________________________________________________________________________
10-Bit Bus LVDS Deserializers
Test Circuits/Timing Diagrams (continued)
tDSR1 (2048 + 42)tRFCP tRFCP RI tZHLK LOCK HIGH-Z RCLK ROUT_ HIGH-Z HIGH-Z 2048 x tRFCP 42 x tRFCP SYNC
MAX9206/MAX9208
PWRDN REFCLK
SYNC PATTERNS
111111 000000
DATA DON'T CARE tDD HIGH-Z HIGH-Z tHZR OR tLZR DATA HIGH-Z
tRCP
RCLK_R/F = LOW
Figure 7. PLL Lock Time from PWRDN
REFCLK tRFCP RI SYNC PATTERNS
111111 000000
DATA
tDD LOCK tDSR2 RCLK tRCP ROUT_ SYNC DATA RCLK_R/F = LOW DATA DATA 42tRFCP
Figure 8. Deserializer PLL Lock Time from Sync Patterns
_______________________________________________________________________________________
7
10-Bit Bus LVDS Deserializers MAX9206/MAX9208
Detailed Description
The MAX9206/MAX9208 deserialize a BLVDS serializer's output into 10-bit wide parallel LVCMOS/LVTTL data and a parallel rate clock. The MAX9206/MAX9208 include a PLL that locks to the frequency and phase of the serial input, and digital circuits that deserialize and deframe the data. The MAX9206/MAX9208 have highinput jitter tolerance while receiving data at speeds from 160Mbps to 600Mbps. Combination with the MAX9205/MAX9207 BLVDS serializers allows data transmission across backplanes using PC board traces, or across twin-ax or twisted-pair cables. The MAX9206/MAX9208 deserializers provide a powersaving, power-down mode when PWRDN is driven low. The output enable, REN, allows the parallel data outputs (ROUT_) and recovered clock (RCLK) to be enabled or disabled while maintaining lock to the serial input. LOCK, along with RCLK, indicates when data is valid at ROUT_. Parallel, deserialized data at ROUT_ is strobed out on the selected strobe edge of RCLK. The strobe edge of RCLK is programmable. The falling edge is selected when RCLK_R/F is low and the rising edge is selected when RCLK_R/F is high. The interface may be point-to-point or a heavily loaded bus. The characteristic impedance of the media and connections can range from 100 for a point-to-point interface to 54 for a heavily loaded bus. A double-terminated point-to-point interface uses a 100 termination resistor at each end of the interface, resulting in a total load of 50. A heavily loaded bus with a termination as low as 54 at each end of the bus (resulting in a total load of 27) can be driven. A high state bit and a low state bit, added by the BLVDS serializer, frame each 10 bits of serial data and create a guaranteed transition for clock recovery. The high bit is prepended at the start and the low bit is appended at the end of the 10-bit data. The rising edge formed at the end/start bit boundary functions as an embedded clock. Twelve serial bits (10 data + 2 frame) are transmitted by the serializer and received by the deserializer for each 10 bits of data transferred. The MAX9206 accepts a 16MHz to 40MHz reference clock, and receives serial data at 160Mbps (10 data bits x 16MHz) to 400Mbps (10 data bits x 40MHz). The MAX9208 accepts a 40MHz to 60MHz reference clock, and receives serial data at a rate of 400Mbps to 600Mbps. impedance, LOCK goes high, and the on-chip PLL locks to REFCLK in 2048 cycles. After locking to REFCLK, ROUT_ is active, RCLK tracks REFCLK, and LOCK remains high. If transitions are detected at the serial input, the PLL locks to the phase and frequency of the serial input, finds the frame bits, and drives LOCK low. If the serial input is sync patterns, LOCK goes low in 42 or fewer cycles of RCLK. When LOCK goes low, RCLK switches from tracking REFCLK to tracking the serializer reference clock (TCLK). Deserialized data at ROUT_ is valid on the second selected strobe edge of RCLK after LOCK goes low. Initialization restarts when power is cycled or on the rising edge of PWRDN. Lock to Pseudorandom Data The MAX9206/MAX9208 lock to pseudorandom serial input data by deductively eliminating rising edges due to data until the embedded end/start edge is found. The end/start edge is identified unless the data contains a permanent, consecutive, frame-to-frame rising edge at the same bit position. Send sync patterns to guarantee lock. A sync pattern is six consecutive ones followed by six consecutive zeros, repeating every RCLK period with only one rising edge (at the end/start boundary). The MAX9205/MAX9207 serializers generate sync patterns when SYNC1 or SYNC2 is driven high. Since sending sync patterns to initialize a deserializer disrupts data transfer to all deserializers receiving the same serial input (Figure 11, for example), lock to pseudorandom data is preferred in many applications. Lock to pseudorandom data allows initialization of a deserializer after hot insertion without disrupting data communication on other links. The MAX9206/MAX9208s' deductive algorithm provides very fast pseudorandom data lock times. Table 1 compares typical lock times for pseudorandom and sync pattern inputs.
Power-Down
Drive PWRDN low to enter the power-down mode. In power-down, the PLL is stopped and the outputs (ROUT_, RCLK, and LOCK) are put in high impedance, disabling drive current and also reducing supply current.
Output Enable
When the deserializer is initialized and REN is high, ROUT_ is active, RCLK tracks the serializer reference clock (TCLK), and LOCK is low. Driving REN low disables the ROUT_ and RCLK output drivers and does not affect state machine timing. ROUT_ and RCLK go
Initialization
Initialize the MAX9206/MAX9208 before receiving data. When power is applied, with REFCLK stable and PWRDN high, RCLK and ROUT_ are held in high
8
_______________________________________________________________________________________
10-Bit Bus LVDS Deserializers MAX9206/MAX9208
Table 1. Typical Lock Times
REFCLK FREQUENCY DATA PATTERN Maximum Maximum (Clock Cycles) Average Average (Clock Cycles) Minimum Minimum (Clock Cycles) 16MHz PSEUDORANDOM DATA 0.749s 11.99 0.318s 5.09 0.13s 2.08 35MHz PSEUDORANDOM DATA 0.375s 13.14 0.158s 5.52 0.068s 2.37 40MHz PSEUDORANDOM DATA 0.354s 14.18 0.144s 5.76 0.061s 2.44 40MHz SYNC PATTERNS 0.134s 5.37 0.103s 4.11 0.061s 2.45
Note: Pseudorandom lock performed with 215-1 PRBS pattern, 10,000 lock time tests.
into high impedance but LOCK continues to reflect the status of the serial input. Driving REN high again enables the ROUT_ and RCLK drivers.
Losing Lock on Serial Data
If one embedded clock edge (rising edge formed by end/start bits) is not detected, LOCK goes high, RCLK tracks REFCLK, and ROUT_ stays active but with invalid data. LOCK stays high for a minimum of two RCLK cycles. Then, if transitions are detected at the serial input, the PLL attempts to lock to the serial input. When the PLL locks to serial input data, LOCK goes low, RCLK tracks the serializer reference clock (TCLK), and ROUT_ is valid on the second selected strobe edge of RCLK after LOCK goes low. A minimum of two embedded clock edges in a row are required to regain lock to the serial input after LOCK goes high. For automatic resynchronization, LOCK can be connected to the MAX9205/MAX9207 serializer SYNC1 or SYNC2 input. With this connection, when LOCK goes high, the serializer sends sync patterns until the deserializer locks to the serial input and drives LOCK low.
detected in spite of LOCK switching since LOCK is high long enough to be sampled (LOCK is high for at least two RCLK cycles after a missed clock edge and RCLK keeps running, allowing sampling). If it is required that LOCK remain high for an undriven input, the on-chip fail-safe circuit can be supplemented with external pullup bias resistors.
Deserializer Jitter Tolerance
The tJT parameter specifies the total zero-to-peak input jitter the deserializer can tolerate before a sampling error occurs (Figure 9). Zero-to-peak jitter is measured from the mean value of the deterministic jitter distribution. Sources of jitter include the serializer (supply noise, reference clock jitter, pulse skew, and intersymbol interference), the interconnect (intersymbol interference, crosstalk, within-pair skew, ground shift), and the deserializer (supply noise). The sum of the zero-to-peak individual jitter sources must be less than or equal to the minimum value of tJT. For example, at 40MHz, the MAX9205 serializer has 140ps (p-p) maximum deterministic output jitter. The zero-to-peak value is 140ps/2 = 70ps. If the interconnect jitter is 100ps (p-p) with a symmetrical distribution, the zero-to-peak jitter is 50ps. The MAX9206 deserializer jitter tolerance is 720ps at 40MHz. The total zero-topeak input jitter is 70ps + 50ps = 120ps, which is less than the jitter tolerance. In this case, the margin is 720ps - 120ps = 600ps.
Input Fail-Safe
When the serial input is undriven (a disconnected cable or serializer output in high impedance, for example) an on-chip fail-safe circuit (Figure 2) drives the serial input high. The response time of the fail-safe circuit depends on interconnect characteristics. With an undriven input, LOCK may switch high and low until the fail-safe circuit takes effect. The undriven condition of the link can be
_______________________________________________________________________________________
9
10-Bit Bus LVDS Deserializers MAX9206/MAX9208
t RCP /12
simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by a differential receiver.
t JT
t JT
V ID = 150mV
Figure 9. Input Jitter Tolerance
Applications Information
Power-Supply Bypassing
Bypass each supply pin with high-frequency surfacemount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smaller valued capacitor the closest to the supply pin.
Eliminate reflections and ensure that noise couples as common mode by running differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90 turns and minimize the number of vias to further prevent impedance discontinuities.
SERIALIZED DATA PARALLEL DATA IN 100 100 PARALLEL DATA OUT
Differential Traces and Termination
Trace characteristics affect the performance of the MAX9206/MAX9208. Use controlled-impedance media. Avoid the use of unbalanced cables such as ribbon or
MAX9205 MAX9207
MAX9206 MAX9208
Figure 10. Double-Termination Point-to-Point
ASIC
ASIC
ASIC
MAX9205 MAX9207
MAX9206 MAX9208
MAX9206 MAX9208
MAX9150 REPEATER
100
100
100
100
Figure 11. Point-to-Point Broadcast Using MAX9150 Repeater 10 _____________________________________________________________________________________
10-Bit Bus LVDS Deserializers MAX9206/MAX9208
Table 2. Input/Output Function Table
LOGIC INPUTS REN X Low High PWRDN Low High High CONDITIONS Power applied and stable Deserializer initialized Deserializer initialized OUTPUTS Power-down mode. PLL is stopped. Current consumption is reduced to 400A (typ). ROUT_, RCLK, and LOCK are high impedance. RCLK and ROUT_ are high impedance. LOCK is active, indicating the serial input status. RCLK and ROUT_ are active. LOCK is active, indicating the serial input status.
X = don't care
Topologies
The MAX9206/MAX9208 deserializers can operate in a variety of topologies. Examples of double-terminated point-to-point and point-to-point broadcast are shown in Figures 10 and 11. Use 1% surface-mount termination resistors. A point-to-point interface terminated at each end in the characteristic impedance of the cable or PC board traces is shown in Figure 10. The total load seen by the serializer is 50. The double termination typically reduces reflections compared to a single 100 termination. A single 100 termination at the deserializer input is feasible and makes the differential signal swing larger. A point-to-point version of a multidrop bus is shown in Figure 11. The low-jitter MAX9150 10-port repeater is used to reproduce and transmit the serializer output over 10 double-terminated point-to-point links. Compared to a bus, more interconnect is traded for robust hot-plug capability. The repeater eliminates nine serializers compared to 10 individual point-to-point serializer-to-deserializer connections. Since repeater jitter is a component of the total jitter seen at the deserializer input (along with other sources of jitter), a low-jitter repeater is essential in most high data-rate applications.
TOP VIEW
AGND 1 RCLK_R/F 2 REFCLK 3 AVCC 4 RI+ 5 RI- 6 PWRDN 7 REN 8 RCLK 9 LOCK 10 AVCC 11 AGND 12 AGND 13 DGND 14
Pin Configuration
28 ROUT0 27 ROUT1 26 ROUT2 25 ROUT3 24 ROUT4
MAX9206/ MAX9208
23 DVCC 22 DGND 21 DVCC 20 DGND 19 ROUT5 18 ROUT6 17 ROUT7 16 ROUT8 15 ROUT9
SSOP
Chip Information
TRANSISTOR COUNT: 9602 PROCESS: CMOS
Board Layout
A four-layer PC board providing separate power, ground, and signal layers is recommended. Keep the LVTTL/LVCMOS inputs and outputs separated from the BLVDS inputs to prevent coupling into the BLVDS lines.
______________________________________________________________________________________
11
10-Bit Bus LVDS Deserializers MAX9206/MAX9208
Package Information
SSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX9206

	To Download MAX9206 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .